Die space on integrated circuits is precious. This is primarily for two reasons. First, the larger the die the lower the yield rate and the higher the cost. Second, because the realistic maximum die size is bounded by an economically acceptable yield rate, the amount of functionality—which largely translates into performance—is limited by the amount of circuitry that can be placed on the die. This is particularly true for highly complex integrated circuits such as microprocessors.
The trend in microprocessor design is toward multi-core microprocessors. That is, each microprocessor includes multiple processing cores on a single integrated circuit. Typically, the multiple processing cores are essentially identical designs replicated on the die, although the multiple cores may share resources that are not within any of the cores. A common example of such a shared resource is a level-2 cache memory. The replication of a processing core multiple times on an integrated circuit creates the need for each core to be as small as possible, since each circuit in the processing core design will typically be replicated multiple times, not uncommonly four or more.